Other lithography approaches offer alternatives

Most semiconductor lithography involves projecting a mask pattern onto a photoresist coated wafer, developing the exposed resist, and using that resist to transfer the pattern onto layers of insulators, conductors, and other circuit elements on the wafer. Repeating this process over and over eventually creates a complete integrated circuit like a microprocessor or memory. However, in their quest to cut costs while patterning finer and finer features, chip makers are looking at alternatives, with some discussed at the 2025 SPIE Advanced Lithography + Patterning conference.

In an example of such work, Tomohiro Iwaki, a Micron Technology principal engineer, spoke about nanoimprint technology issues and outlook. In this patterning approach, a template mask, an analog to the one in projection lithography, is pressed like a stamp onto a resin applied as inkjet drops to the wafer surface. UV light cures the resin, hardening it. Then the mask is removed, and processing continues in the same fashion as it would for a wafer patterned with projection lithography.

Micron Technology has been researching nanoimprinting for years, and its latest results indicate a handful of challenges. The biggest issue, Iwaki noted, is a high number of defects after patterning, with these faults both random from die to die and repeated from die to die. Even one defect can kill a logic circuit. Memory chips, in contrast, can be built with redundant structures and so can effectively heal defects by swapping out an extra circuit for a bad one. But there are limits to such fault correction.

Another issue Iwaki mentioned is a too-short lifetime for the template mask. Solving one of these issues will solve the other.

“Overcoming the defect challenges will increase the lifetime of the mask,” Iwaki said.

He added several avenues exist to reduce defect levels. These include changing the surface material of the template mask, reducing particles in the inkjet resist, making it easier to peel the mask from the exposed resist, and other chemistry changes that improve the process.

He noted that nanoimprinting has primarily been examined to scale down feature sizes. However, Iwaki said it also allows the creation of shapes not possible with the latest projection lithography, extreme ultraviolet lithography.

Florian Gstrein, a senior principal engineer at Intel, presented a paper on another alternative lithography technique: directed self-assembly. In this approach, fabricators pattern a special coating on a wafer. That coating causes one set of molecules to stick to it. A second, complementary set of molecules then stick to the first. When subjected to a bit of heat, the result is the molecules line up, assembling themselves into a pattern that replicates that of the special coating.

Due to the chemistry involved, that replication is almost perfect. “Defectivity is not a concern for the use of directed self-assembly,” Gstrein said.

The two sets of molecules that lock together like Legos have a characteristic length, which is set during the synthesis of the molecules. Anything smaller than that length is ignored, Gstrein noted.

This attribute can be helpful when patterning repeated lines and spaces. Even a noisy initial template pattern, such as one where random, or stochastic, events cause line edges to be rough and ragged, is cleaned up nearly perfectly by directed self-assembly. Stochastic-driven effects are a major concern in EUV lithography.

Simulations show that adding directed self-assembly to an advanced EUV patterning process can boost yields out of that process by about 10 percent. The improvement arises because of reduced variability from line to line and space to space.

But directed self-assembly’s strength is also its weakness. The technique could be a good fit for semiconductor memories, which have large arrays of regularly repeated and uniform standard memory cells. Logic, the circuitry that does calculations and takes actions based on what’s in those memory cells, has a much more random layout full of irregular structure.

“It’s not a technique that’s going to be applicable to every segment,” Gstrein said when discussing this in a Q &A after his presentation.

Hence, directed self-assembly might be used for some chips or parts of chips, while not being deployed elsewhere in the fabrication process.

Hank Hogan is a freelance science and technology writer.